The present invention generally relates to semiconductor devices and more particularly to fabricating semiconductor structures having a gate stack that may prevent unwanted diffusion to a gate dielectric interface.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FET) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET), in which a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel through the channel region between a source region and a drain region of the substrate. The gate structure may be formed above the channel region and may generally include a gate dielectric layer as a part of or underneath other gate elements. The gate dielectric layer may include an insulator material, which may prevent leakage currents from flowing into the channel region when a voltage is applied to a gate electrode, while allowing the applied voltage to set up a transverse electric field in the channel region in a controllable manner.
In a replacement metal gate (RMG) fabrication approach, a dummy gate may be formed in the substrate. The dummy gate may be patterned and etched from a polysilicon layer above the substrate, over a portion of one or more fins formed from the substrate. In some cases, the dummy gate may be formed surrounding a nanowire or above a semiconductor-on-insulator (SOI) substrate. Gate spacers may be formed on opposite sidewalls of the dummy gate. The dummy gate and the gate spacers may then be surrounded by an interlevel dielectric (ILD) layer. Later, the dummy gate may be removed from between the gate spacers, as by, for example, an anisotropic vertical etch process such as a reactive ion etch (RIE). This may create a recess between the gate spacers where a metal gate, or gate electrode, may then be formed. A gate dielectric layer may be generally configured below the metal gate, although one or more layers of workfunction metals may be generally located between the gate dielectric layer and the metal gate. This sequence of layers including the gate dielectric layer, the workfunction metals and the metal gate may be referred to as a metal gate stack.